1. Field of the Invention
The present invention relates to a design method for a semiconductor integrated circuit, and more particularly to a design method for a semiconductor integrated circuit which suppresses power supply noise occurring in a power supply wire.
2. Description of the Background Art
In order to achieve high-speed operation and low power consumption at the same time, semiconductor integrated circuits of recent years adopt a method for controlling a source power supply (ADD) of a P-channel transistor and a substrate power supply (N-well power supply VSUBN) by separate power supplies, or a method for controlling a source power supply (VSS) of an N-channel transistor and a substrate power supply (P-substrate power supply VSUBP) by separate power supplies. Note that “substrate voltage” as described herein refers to a potential which confronts a potential of a gate, which controls the amount of electric charge in a channel of a transistor, and refers to a well voltage in the case of a transistor provided within a well.
FIGS. 12A and 12B are diagrams each showing the structure of a CMOS inverter in which an additional power supply is used to control voltage of a circuit substrate. As shown in FIG. 12A, the above CMOS inverter comprises a P-channel transistor 91 and an N-channel transistor 92. These two transistors each have, in addition to three terminals (i.e., source, drain, and gate terminals), a substrate terminal as a fourth terminal. The drain terminals of the two transistors are connected to each other. The source terminal of the P-channel transistor 91 and the source terminal of the N-channel transistor 92 are connected respectively to a power supply ADD and a ground VSS. The substrate terminal of the P-channel transistor 91 is connected to an N-well power supply VSUBN, and the substrate terminal of the N-channel transistor 92 is connected to a P-substrate power supply VSUBP.
FIG. 12B is a diagram showing a cross-sectional structure of the CMOS inverter. As shown in FIG. 12B, an N-well 94 is provided on one surface of a substrate 93, and the P-channel transistor 91 and the N-channel transistor 92 are provided respectively within the N-well 94 and on the substrate 93. In addition, in the N-well 94, a well contact 95 is provided as the substrate terminal of the P-channel transistor 91, whereas on the substrate 93, a substrate contact 96 is provided as the substrate terminal of the N-channel transistor 92. In many conventional semiconductor integrated circuits, a common power supply is used as the power supply ADD and the N-well power supply VSUBN. In semiconductor integrated circuits of recent years, however, separate power supplies which are substantially the same but different in potential are often used as the power supply ADD and the N-well power supply VSUBN, in order to achieve high-speed operation and low power consumption at the same time. Transistors that operate at high speed usually have a triple-well structure, but for simplification of explanation, a transistor having a twin-well structure is described here.
FIGS. 13A to 13C are graphs each showing the results obtained by measuring power supply noise occurring in the power supply ADD and the N-well power supply VSUBN of the semiconductor integrated circuit in which an additional power supply is used to control voltage of the circuit substrate. The graphs of FIGS. 13A to 13C show how potentials of the power supply ADD (solid lines) and the N-well power supply VSUBN (dashed lines) fluctuate at clock signal frequencies of 50 MHz, 100 MHz, and 200 MHz. From the measurement results shown in FIGS. 13A to 13C, it is apparent that a relative relationship between power supply noise (i.e., potential fluctuation) of the power supply ADD and that of the N-well power supply VSUBN varies with the clock signal frequency in a nonlinear manner. For example, in the case where the clock signal frequency is 100 MHz, the power supply noise of the N-well power supply VSUBN fluctuates more sharply than can be expected from the measurement results obtained in the cases where the clock signal frequencies are 50 MHz and 200 MHz. This is because the impedance of a path including a power supply wire separated by a resistance element, a substrate resistance, and a capacitive element, etc., is minimized when the clock frequency is around 100 MHz (i.e., a resonance frequency is around 100 MHz).
If the power supply noise varies with the clock signal frequency in a nonlinear manner as described above, the operating frequency of the semiconductor integrated circuit and a frequency at which the power supply noise increases might overlap one another. If the semiconductor integrated circuit is caused to operate at such a frequency, power supply noise might increase to change the threshold voltage and operating current of a transistor, so that a delay value and an output potential of the transistor are changed, resulting in malfunction of the transistor. Further, in semiconductor integrated circuits of recent years, with the progress of a fine process technology, it is required to lower power supply voltage. Also, the amount of current flowing through a circuit is increased with the number of transistors. Because of the above reasons, in the semiconductor integrated circuits of recent years, the design margin in relation to power supply fluctuation tends to be insufficient.
However, with conventional transistor-level circuit simulation or substrate noise simulation, it is impossible to analyze power supply noise of a semiconductor integrated circuit in which an additional power supply is used to control voltage of the circuit substrate. Therefore, the applicant of the present application has invented a new method for analyzing power supply noise of a semiconductor integrated circuit which is applicable to the above described semiconductor integrated circuit in which an additional power supply is used to control voltage of the circuit substrate, and filed a patent application (Japanese Patent Application No. 2003-396214) for the above analyzing method.
The following techniques have been known as other conventional techniques relating to the present invention. In U.S. Pat. No. 6,523,150, a method for suppressing IR-Drop (power supply voltage drop), which is a type of power supply noise, is disclosed. In this method, power supply pads are optimally assigned to each region in the semiconductor integrated circuit, and the impedance of a path from the power supply pad to an internal device of the semiconductor integrated circuit is adjusted.
Also, in Japanese Laid-Open Patent Publication No. 2001-202400, a method for suppressing EMI (Electro Magnetic Interference) noise, which is a type of power supply noise, is disclosed. In this method, a decoupling capacitor is inserted between a power supply wire and a ground wire in order to provide a path (low-pass filter) for cutting a high-frequency component. By inserting the decoupling capacitor, the impedance of the power supply wire is adjusted.
However, in the above-described methods, an impedance of a path including a power supply wire separated by a resistance element, a substrate resistance, and a capacitive element, etc., is not adjusted, and a resonance frequency is not controlled. Thus, by the above-described conventional methods, it is impossible to suppress power supply noise by taking into account a frequency characteristic of power supply noise.